Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/isca/KrimerCE12
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dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/isca/KrimerCE12
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Evgeni_Krimer
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Mattan_Erez
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Patrick_Chiang_0001
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FISCA.2012.6237021
>
foaf:
homepage
<
https://doi.org/10.1109/ISCA.2012.6237021
>
dc:
identifier
DBLP conf/isca/KrimerCE12
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FISCA.2012.6237021
(xsd:string)
dcterms:
issued
2012
(xsd:gYear)
rdfs:
label
Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Evgeni_Krimer
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Mattan_Erez
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Patrick_Chiang_0001
>
swrc:
pages
237-248
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/isca/2012
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/isca/KrimerCE12/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/isca/KrimerCE12
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/isca/isca2012.html#KrimerCE12
>
rdfs:
seeAlso
<
https://doi.org/10.1109/ISCA.2012.6237021
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/isca
>
dc:
title
Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document