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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/isca/ZhangA05>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Krste_Asanovic>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Michael_Zhang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISCA.2005.53>
foaf:homepage <https://doi.org/10.1109/ISCA.2005.53>
dc:identifier DBLP conf/isca/ZhangA05 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISCA.2005.53 (xsd:string)
dcterms:issued 2005 (xsd:gYear)
rdfs:label Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Krste_Asanovic>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Michael_Zhang>
swrc:pages 336-345 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/isca/2005>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/isca/ZhangA05/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/isca/ZhangA05>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/isca/isca2005.html#ZhangA05>
rdfs:seeAlso <https://doi.org/10.1109/ISCA.2005.53>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/isca>
dc:title Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document