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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iscas/AliotoPRV06>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Luca_Pancioni>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Massimo_Alioto>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Santina_Rocchi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Valerio_Vignoli>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISCAS.2006.1692822>
foaf:homepage <https://doi.org/10.1109/ISCAS.2006.1692822>
dc:identifier DBLP conf/iscas/AliotoPRV06 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISCAS.2006.1692822 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
rdfs:label Analysis and design of MCML gates with hysteresis. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Luca_Pancioni>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Massimo_Alioto>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Santina_Rocchi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Valerio_Vignoli>
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iscas/2006>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iscas/AliotoPRV06/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iscas/AliotoPRV06>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iscas/iscas2006.html#AliotoPRV06>
rdfs:seeAlso <https://doi.org/10.1109/ISCAS.2006.1692822>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iscas>
dc:title Analysis and design of MCML gates with hysteresis. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document