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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iscas/BolHFL10>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/C%E2%88%9A%C2%A9dric_Hocquet>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/David_Bol>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Denis_Flandre>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jean-Didier_Legat>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISCAS.2010.5537352>
foaf:homepage <https://doi.org/10.1109/ISCAS.2010.5537352>
dc:identifier DBLP conf/iscas/BolHFL10 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISCAS.2010.5537352 (xsd:string)
dcterms:issued 2010 (xsd:gYear)
rdfs:label Robustness-aware sleep transistor engineering for power-gated nanometer subthreshold circuits. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/C%E2%88%9A%C2%A9dric_Hocquet>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/David_Bol>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Denis_Flandre>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jean-Didier_Legat>
swrc:pages 1484-1487 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iscas/2010>
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rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iscas/iscas2010.html#BolHFL10>
rdfs:seeAlso <https://doi.org/10.1109/ISCAS.2010.5537352>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iscas>
dc:title Robustness-aware sleep transistor engineering for power-gated nanometer subthreshold circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document