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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iscas/CardosoSNPNA21>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Erivelton_G._Nepomuceno>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Janier_Arias-Garcia>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Lucas_Giovanni_Nardo>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Matheus_B._R._Cardoso>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Roberto_M._Passos>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Samuel_S._da_Silva>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISCAS51556.2021.9401653>
foaf:homepage <https://doi.org/10.1109/ISCAS51556.2021.9401653>
dc:identifier DBLP conf/iscas/CardosoSNPNA21 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISCAS51556.2021.9401653 (xsd:string)
dcterms:issued 2021 (xsd:gYear)
rdfs:label A New PRNG Hardware Architecture Based on an Exponential Chaotic Map. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Erivelton_G._Nepomuceno>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Janier_Arias-Garcia>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Lucas_Giovanni_Nardo>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Matheus_B._R._Cardoso>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Roberto_M._Passos>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Samuel_S._da_Silva>
swrc:pages 1-5 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iscas/2021>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iscas/CardosoSNPNA21/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iscas/CardosoSNPNA21>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iscas/iscas2021.html#CardosoSNPNA21>
rdfs:seeAlso <https://doi.org/10.1109/ISCAS51556.2021.9401653>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iscas>
dc:title A New PRNG Hardware Architecture Based on an Exponential Chaotic Map. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document