A subthreshold SRAM with embedded data-aware write-assist and adaptive data-aware keeper.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/iscas/ChiuHZJC16
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A subthreshold SRAM with embedded data-aware write-assist and adaptive data-aware keeper.
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A subthreshold SRAM with embedded data-aware write-assist and adaptive data-aware keeper.
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