Design of a 64-bit Low-energy High-performance Adder using Dynamic Feedthrough Logic.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/iscas/ChuangLS09
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Design of a 64-bit Low-energy High-performance Adder using Dynamic Feedthrough Logic.
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Design of a 64-bit Low-energy High-performance Adder using Dynamic Feedthrough Logic.
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