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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iscas/ChungK06>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/B._Chung>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/J._B._Kuo>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISCAS.2006.1693418>
foaf:homepage <https://doi.org/10.1109/ISCAS.2006.1693418>
dc:identifier DBLP conf/iscas/ChungK06 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISCAS.2006.1693418 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
rdfs:label Gate-level dual-threshold static power optimization methodology (GDSPOM) for designing high-speed low-power SOC applications using 90nm MTCMOS technology. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/B._Chung>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/J._B._Kuo>
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iscas/2006>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iscas/ChungK06/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iscas/ChungK06>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iscas/iscas2006.html#ChungK06>
rdfs:seeAlso <https://doi.org/10.1109/ISCAS.2006.1693418>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iscas>
dc:title Gate-level dual-threshold static power optimization methodology (GDSPOM) for designing high-speed low-power SOC applications using 90nm MTCMOS technology. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document