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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iscas/HuangWHC03>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Bing-Yu_Hsieh>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Liang-Gee_Chen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tu-Chih_Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yu-Wen_Huang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISCAS.2003.1206094>
foaf:homepage <https://doi.org/10.1109/ISCAS.2003.1206094>
dc:identifier DBLP conf/iscas/HuangWHC03 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISCAS.2003.1206094 (xsd:string)
dcterms:issued 2003 (xsd:gYear)
rdfs:label Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Bing-Yu_Hsieh>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Liang-Gee_Chen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tu-Chih_Wang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yu-Wen_Huang>
swrc:pages 796-799 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iscas/2003>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iscas/HuangWHC03/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iscas/HuangWHC03>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iscas/iscas2003-2.html#HuangWHC03>
rdfs:seeAlso <https://doi.org/10.1109/ISCAS.2003.1206094>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iscas>
dc:title Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document