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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iscas/JiangSMH12>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jianfei_Jiang_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wei-Feng_He>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wei-Guang_Sheng>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zhi-Gang_Mao>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISCAS.2012.6271933>
foaf:homepage <https://doi.org/10.1109/ISCAS.2012.6271933>
dc:identifier DBLP conf/iscas/JiangSMH12 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISCAS.2012.6271933 (xsd:string)
dcterms:issued 2012 (xsd:gYear)
rdfs:label A pre-emphasis circuit design for high speed on-chip global interconnect. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jianfei_Jiang_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wei-Feng_He>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wei-Guang_Sheng>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zhi-Gang_Mao>
swrc:pages 2941-2944 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iscas/2012>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iscas/JiangSMH12/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iscas/JiangSMH12>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iscas/iscas2012.html#JiangSMH12>
rdfs:seeAlso <https://doi.org/10.1109/ISCAS.2012.6271933>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iscas>
dc:title A pre-emphasis circuit design for high speed on-chip global interconnect. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document