A 65nm Compute-In-Memory 7T SRAM Macro Supporting 4-bit Multiply and Accumulate Operation by Employing Charge Sharing.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/iscas/KushwahaSGRJMKM22
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A 65nm Compute-In-Memory 7T SRAM Macro Supporting 4-bit Multiply and Accumulate Operation by Employing Charge Sharing.
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