Architecture of a multi-slot main memory system for 3.2 Gbps operation.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/iscas/LeeLPN10
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dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/iscas/LeeLPN10
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Jaejun_Lee
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Joontae_Park
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Sangwook_Nam
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Sungho_Lee
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FISCAS.2010.5537702
>
foaf:
homepage
<
https://doi.org/10.1109/ISCAS.2010.5537702
>
dc:
identifier
DBLP conf/iscas/LeeLPN10
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FISCAS.2010.5537702
(xsd:string)
dcterms:
issued
2010
(xsd:gYear)
rdfs:
label
Architecture of a multi-slot main memory system for 3.2 Gbps operation.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Jaejun_Lee
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Joontae_Park
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Sangwook_Nam
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Sungho_Lee
>
swrc:
pages
3857-3860
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/iscas/2010
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/iscas/LeeLPN10/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/iscas/LeeLPN10
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/iscas/iscas2010.html#LeeLPN10
>
rdfs:
seeAlso
<
https://doi.org/10.1109/ISCAS.2010.5537702
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/iscas
>
dc:
title
Architecture of a multi-slot main memory system for 3.2 Gbps operation.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document