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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iscas/LimaPRRMCCSB19>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Eduardo_A._C._da_Costa>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Felipe_S._Marques_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Guilherme_Paim>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Leandro_M._G._Rocha>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Leomar_S._da_Rosa_Jr.>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rafael_Soares>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sergio_Bampi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vinicius_V._Camargo>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vitor_G._Lima>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISCAS.2019.8702687>
foaf:homepage <https://doi.org/10.1109/ISCAS.2019.8702687>
dc:identifier DBLP conf/iscas/LimaPRRMCCSB19 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISCAS.2019.8702687 (xsd:string)
dcterms:issued 2019 (xsd:gYear)
rdfs:label Maximizing Side Channel Attack-Resistance and Energy-Efficiency of the STTL Combining Multi-Vt Transistors with Current and Capacitance Balancing. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Eduardo_A._C._da_Costa>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Felipe_S._Marques_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Guilherme_Paim>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Leandro_M._G._Rocha>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Leomar_S._da_Rosa_Jr.>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rafael_Soares>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sergio_Bampi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vinicius_V._Camargo>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vitor_G._Lima>
swrc:pages 1-5 (xsd:string)
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owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iscas/LimaPRRMCCSB19>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iscas/iscas2019.html#LimaPRRMCCSB19>
rdfs:seeAlso <https://doi.org/10.1109/ISCAS.2019.8702687>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iscas>
dc:title Maximizing Side Channel Attack-Resistance and Energy-Efficiency of the STTL Combining Multi-Vt Transistors with Current and Capacitance Balancing. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document