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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iscas/LiuZZCC23>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jienan_Chen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tianchi_Liu_0005>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yakun_Zhou>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yizhuo_Zhou>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zheng_Chai>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISCAS46773.2023.10181471>
foaf:homepage <https://doi.org/10.1109/ISCAS46773.2023.10181471>
dc:identifier DBLP conf/iscas/LiuZZCC23 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISCAS46773.2023.10181471 (xsd:string)
dcterms:issued 2023 (xsd:gYear)
rdfs:label Hardware Efficient Reconfigurable Logic-in-Memory Circuit Based Neural Network Computing. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jienan_Chen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tianchi_Liu_0005>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yakun_Zhou>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yizhuo_Zhou>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zheng_Chai>
swrc:pages 1-5 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iscas/2023>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iscas/LiuZZCC23/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iscas/LiuZZCC23>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iscas/iscas2023.html#LiuZZCC23>
rdfs:seeAlso <https://doi.org/10.1109/ISCAS46773.2023.10181471>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iscas>
dc:title Hardware Efficient Reconfigurable Logic-in-Memory Circuit Based Neural Network Computing. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document