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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iscas/LuYYXLW17>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Leibo_Liu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shaojun_Wei>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shouyi_Yin>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tianyi_Lu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xianqing_Yao>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zhicong_Xie>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISCAS.2017.8050969>
foaf:homepage <https://doi.org/10.1109/ISCAS.2017.8050969>
dc:identifier DBLP conf/iscas/LuYYXLW17 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISCAS.2017.8050969 (xsd:string)
dcterms:issued 2017 (xsd:gYear)
rdfs:label Memory fartitioning-based modulo scheduling for high-level synthesis. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Leibo_Liu>
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foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shouyi_Yin>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tianyi_Lu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xianqing_Yao>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zhicong_Xie>
swrc:pages 1-4 (xsd:string)
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rdfs:seeAlso <https://doi.org/10.1109/ISCAS.2017.8050969>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iscas>
dc:title Memory fartitioning-based modulo scheduling for high-level synthesis. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document