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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iscas/Mashreghi-Moghadamy22>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Parisa_Mashreghi-Moghadam>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tarek_Ould-Bachir>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yvon_Savaria>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISCAS48785.2022.9937607>
foaf:homepage <https://doi.org/10.1109/ISCAS48785.2022.9937607>
dc:identifier DBLP conf/iscas/Mashreghi-Moghadamy22 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISCAS48785.2022.9937607 (xsd:string)
dcterms:issued 2022 (xsd:gYear)
rdfs:label A Templated VHDL Architecture for Terabit/s P4-programmable FPGA-based Packet Parsing. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Parisa_Mashreghi-Moghadam>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tarek_Ould-Bachir>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yvon_Savaria>
swrc:pages 672-676 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iscas/2022>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iscas/Mashreghi-Moghadamy22/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iscas/Mashreghi-Moghadamy22>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iscas/iscas2022.html#Mashreghi-Moghadamy22>
rdfs:seeAlso <https://doi.org/10.1109/ISCAS48785.2022.9937607>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iscas>
dc:title A Templated VHDL Architecture for Terabit/s P4-programmable FPGA-based Packet Parsing. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document