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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iscas/MohieldinES02>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/A._N._Mohieldin>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ahmed_Emira>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Edgar_S%E2%88%9A%C2%B0nchez-Sinencio>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISCAS.2002.1010544>
foaf:homepage <https://doi.org/10.1109/ISCAS.2002.1010544>
dc:identifier DBLP conf/iscas/MohieldinES02 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISCAS.2002.1010544 (xsd:string)
dcterms:issued 2002 (xsd:gYear)
rdfs:label A 2-V 11-bit incremental A/D converter using floating gate technique. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/A._N._Mohieldin>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ahmed_Emira>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Edgar_S%E2%88%9A%C2%B0nchez-Sinencio>
swrc:pages 667-670 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iscas/2002>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iscas/MohieldinES02/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iscas/MohieldinES02>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iscas/iscas2002-4.html#MohieldinES02>
rdfs:seeAlso <https://doi.org/10.1109/ISCAS.2002.1010544>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iscas>
dc:title A 2-V 11-bit incremental A/D converter using floating gate technique. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document