Simple improvement stage for low voltage WTA and Rank Order circuits. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Alejandra_Morales-Ramirez>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Jaime_Ram%E2%88%9A%E2%89%A0rez-Angulo>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Jesus_E._Molinar-Solis>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Rodolfo_Garcia-Lozano>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FISCAS.2011.5937708>
foaf:homepage	<https://doi.org/10.1109/ISCAS.2011.5937708>
dc:identifier	DBLP conf/iscas/Molinar-SolisGMR11 (xsd:string)
dc:identifier	DOI doi.org%2F10.1109%2FISCAS.2011.5937708 (xsd:string)
dcterms:issued	2011 (xsd:gYear)
rdfs:label	Simple improvement stage for low voltage WTA and Rank Order circuits. (xsd:string)
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foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Jesus_E._Molinar-Solis>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Rodolfo_Garcia-Lozano>
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dc:title	Simple improvement stage for low voltage WTA and Rank Order circuits. (xsd:string)
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