Design of a 5-bit Signed SRAM-based In-Memory Computing Cell for Deep Learning Models.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/iscas/Pereira-RialG0L22
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Design of a 5-bit Signed SRAM-based In-Memory Computing Cell for Deep Learning Models.
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Design of a 5-bit Signed SRAM-based In-Memory Computing Cell for Deep Learning Models.
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