[RDF data]
Home | Example Publications
PropertyValue
dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iscas/ReddySA14>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Amit_Acharyya>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Basireddy_Karunakar_Reddy>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Srinivas_Sabbavarapu>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISCAS.2014.6865094>
foaf:homepage <https://doi.org/10.1109/ISCAS.2014.6865094>
dc:identifier DBLP conf/iscas/ReddySA14 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISCAS.2014.6865094 (xsd:string)
dcterms:issued 2014 (xsd:gYear)
rdfs:label A new VLSI IC design automation methodology with reduced NRE costs and time-to-market using the NPN class Representation and functional symmetry. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Amit_Acharyya>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Basireddy_Karunakar_Reddy>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Srinivas_Sabbavarapu>
swrc:pages 177-180 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iscas/2014>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iscas/ReddySA14/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iscas/ReddySA14>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iscas/iscas2014.html#ReddySA14>
rdfs:seeAlso <https://doi.org/10.1109/ISCAS.2014.6865094>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iscas>
dc:title A new VLSI IC design automation methodology with reduced NRE costs and time-to-market using the NPN class Representation and functional symmetry. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document