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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iscas/SaitoMHTSAKM05>
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dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kazuya_Tanigawa>
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dc:creator <https://dblp.l3s.de/d2r/resource/authors/Moto_Maeda>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tadashi_Saito>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tetsuo_Hironaka>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tetsushi_Koide>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tetsuya_Sueyoshi>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISCAS.2005.1465385>
foaf:homepage <https://doi.org/10.1109/ISCAS.2005.1465385>
dc:identifier DBLP conf/iscas/SaitoMHTSAKM05 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISCAS.2005.1465385 (xsd:string)
dcterms:issued 2005 (xsd:gYear)
rdfs:label Design of superscalar processor with multi-bank register file. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hans_J%E2%88%9A%C4%BErgen_Mattausch>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kazuya_Tanigawa>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ken-ichi_Aoyama>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Moto_Maeda>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tadashi_Saito>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tetsuo_Hironaka>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tetsushi_Koide>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tetsuya_Sueyoshi>
swrc:pages 3507-3510 (xsd:string)
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rdfs:seeAlso <https://doi.org/10.1109/ISCAS.2005.1465385>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iscas>
dc:title Design of superscalar processor with multi-bank register file. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document