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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iscas/SarkarPDBB08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ravi_Sankar_Prasad>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sanjoy_Kumar_Dey>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Santanu_Sarkar_0002>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Swapna_Banerjee>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vinay_Belde>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISCAS.2008.4541376>
foaf:homepage <https://doi.org/10.1109/ISCAS.2008.4541376>
dc:identifier DBLP conf/iscas/SarkarPDBB08 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISCAS.2008.4541376 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
rdfs:label An 8-bit 1.8 V 500 MS/s CMOS DAC with a novel four-stage current steering architecture. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ravi_Sankar_Prasad>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sanjoy_Kumar_Dey>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Santanu_Sarkar_0002>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Swapna_Banerjee>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vinay_Belde>
swrc:pages 149-152 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iscas/2008>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iscas/SarkarPDBB08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iscas/SarkarPDBB08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iscas/iscas2008.html#SarkarPDBB08>
rdfs:seeAlso <https://doi.org/10.1109/ISCAS.2008.4541376>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iscas>
dc:title An 8-bit 1.8 V 500 MS/s CMOS DAC with a novel four-stage current steering architecture. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document