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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iscas/StasB17>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/David_Bol>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Fran%E2%88%9A%C3%9Fois_Stas>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISCAS.2017.8050571>
foaf:homepage <https://doi.org/10.1109/ISCAS.2017.8050571>
dc:identifier DBLP conf/iscas/StasB17 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISCAS.2017.8050571 (xsd:string)
dcterms:issued 2017 (xsd:gYear)
rdfs:label Integration of level shifting in a TSPC flip-flop for low-power robust timing closure in dual-Vdd ULV circuits. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/David_Bol>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Fran%E2%88%9A%C3%9Fois_Stas>
swrc:pages 1-4 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iscas/2017>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iscas/StasB17/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iscas/StasB17>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iscas/iscas2017.html#StasB17>
rdfs:seeAlso <https://doi.org/10.1109/ISCAS.2017.8050571>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iscas>
dc:title Integration of level shifting in a TSPC flip-flop for low-power robust timing closure in dual-Vdd ULV circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document