The design of a 1 V, 40 MHz, current-mode sample-and-hold circuit with 10-bit linearity.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/iscas/SugimotoI99
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The design of a 1 V, 40 MHz, current-mode sample-and-hold circuit with 10-bit linearity.
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The design of a 1 V, 40 MHz, current-mode sample-and-hold circuit with 10-bit linearity.
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