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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iscas/WassatschT01>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Andreas_Wassatsch>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Dirk_Timmermann>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISCAS.2001.922178>
foaf:homepage <https://doi.org/10.1109/ISCAS.2001.922178>
dc:identifier DBLP conf/iscas/WassatschT01 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISCAS.2001.922178 (xsd:string)
dcterms:issued 2001 (xsd:gYear)
rdfs:label Scalable counter architecture for a pre-loadable 1 GHz@0.6 um/5V pre-scaler in TSPC. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Andreas_Wassatsch>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Dirk_Timmermann>
swrc:pages 92-95 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iscas/2001>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iscas/WassatschT01/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iscas/WassatschT01>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iscas/iscas2001-4.html#WassatschT01>
rdfs:seeAlso <https://doi.org/10.1109/ISCAS.2001.922178>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iscas>
dc:title Scalable counter architecture for a pre-loadable 1 GHz@0.6 um/5V pre-scaler in TSPC. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document