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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iscas/YanamanamandaLW05>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Janet_Meiling_Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jun_Li_0066>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Satish_K._Yanamanamanda>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISCAS.2005.1465123>
foaf:homepage <https://doi.org/10.1109/ISCAS.2005.1465123>
dc:identifier DBLP conf/iscas/YanamanamandaLW05 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISCAS.2005.1465123 (xsd:string)
dcterms:issued 2005 (xsd:gYear)
rdfs:label Uncertainty modeling of gate delay considering multiple input switching. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Janet_Meiling_Wang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jun_Li_0066>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Satish_K._Yanamanamanda>
swrc:pages 2457-2460 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iscas/2005>
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owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iscas/YanamanamandaLW05>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iscas/iscas2005-3.html#YanamanamandaLW05>
rdfs:seeAlso <https://doi.org/10.1109/ISCAS.2005.1465123>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iscas>
dc:title Uncertainty modeling of gate delay considering multiple input switching. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document