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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iscas/ZhouL07>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Dajiang_Zhou>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Peilin_Liu>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISCAS.2007.377858>
foaf:homepage <https://doi.org/10.1109/ISCAS.2007.377858>
dc:identifier DBLP conf/iscas/ZhouL07 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISCAS.2007.377858 (xsd:string)
dcterms:issued 2007 (xsd:gYear)
rdfs:label A Hardware-Efficient Dual-Standard VLSI Architecture for MC Interpolation in AVS and H.264. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Dajiang_Zhou>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Peilin_Liu>
swrc:pages 2910-2913 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iscas/2007>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iscas/ZhouL07/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iscas/ZhouL07>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iscas/iscas2007.html#ZhouL07>
rdfs:seeAlso <https://doi.org/10.1109/ISCAS.2007.377858>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iscas>
dc:title A Hardware-Efficient Dual-Standard VLSI Architecture for MC Interpolation in AVS and H.264. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document