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dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chandan_Kumar_Sarkar>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Dipankar_Saha>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sagar_Mukherjee>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sayan_Chatterjee>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Subhramita_Basak>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISED.2012.23>
foaf:homepage <https://doi.org/10.1109/ISED.2012.23>
dc:identifier DBLP conf/ised/BasakSMCS12 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISED.2012.23 (xsd:string)
dcterms:issued 2012 (xsd:gYear)
rdfs:label Design and Analysis of a Robust, High Speed, Energy Efficient 18 Transistor 1-bit Full Adder Cell, Modified with the Concept of MVT Scheme. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chandan_Kumar_Sarkar>
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foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sagar_Mukherjee>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sayan_Chatterjee>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Subhramita_Basak>
swrc:pages 130-134 (xsd:string)
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rdfs:seeAlso <https://doi.org/10.1109/ISED.2012.23>
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dc:title Design and Analysis of a Robust, High Speed, Energy Efficient 18 Transistor 1-bit Full Adder Cell, Modified with the Concept of MVT Scheme. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document