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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ised/DennisPVASMR17>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Arijit_Mondal>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ayushi_Priyam>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Don_Kurian_Dennis>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kailash_Chandra_Ray>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sajal_Agrawal>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sukhpreet_Singh_Virk>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tanuj_Sharma>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISED.2017.8303926>
foaf:homepage <https://doi.org/10.1109/ISED.2017.8303926>
dc:identifier DBLP conf/ised/DennisPVASMR17 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISED.2017.8303926 (xsd:string)
dcterms:issued 2017 (xsd:gYear)
rdfs:label Single cycle RISC-V micro architecture processor and its FPGA prototype. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Arijit_Mondal>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ayushi_Priyam>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Don_Kurian_Dennis>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kailash_Chandra_Ray>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sajal_Agrawal>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sukhpreet_Singh_Virk>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tanuj_Sharma>
swrc:pages 1-5 (xsd:string)
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rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ised/ised2017.html#DennisPVASMR17>
rdfs:seeAlso <https://doi.org/10.1109/ISED.2017.8303926>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ised>
dc:title Single cycle RISC-V micro architecture processor and its FPGA prototype. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document