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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ised/SangeethaRPPT18>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Basavaraj_Talawar>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/G._S._Sangeetha>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Khyamling_Parane>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Prabhu_B._M._Prasad>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vignesh_Radhakrishnan>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISED.2018.8703884>
foaf:homepage <https://doi.org/10.1109/ISED.2018.8703884>
dc:identifier DBLP conf/ised/SangeethaRPPT18 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISED.2018.8703884 (xsd:string)
dcterms:issued 2018 (xsd:gYear)
rdfs:label Trace-Driven Simulation and Design Space Exploration of Network-on-Chip Topologies on FPGA. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Basavaraj_Talawar>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/G._S._Sangeetha>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Khyamling_Parane>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Prabhu_B._M._Prasad>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vignesh_Radhakrishnan>
swrc:pages 129-134 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ised/2018>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ised/SangeethaRPPT18/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ised/SangeethaRPPT18>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ised/ised2018.html#SangeethaRPPT18>
rdfs:seeAlso <https://doi.org/10.1109/ISED.2018.8703884>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ised>
dc:title Trace-Driven Simulation and Design Space Exploration of Network-on-Chip Topologies on FPGA. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document