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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ises/JagwaniVV15>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Neha_Jagwani>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Santosh_Kumar_Vishvakarma>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vikas_Vijayvargiya>
foaf:homepage <http://dx.doi.org/doi.ieeecomputersociety.org%2F10.1109%2FiNIS.2015.22>
foaf:homepage <https://doi.ieeecomputersociety.org/10.1109/iNIS.2015.22>
dc:identifier DBLP conf/ises/JagwaniVV15 (xsd:string)
dc:identifier DOI doi.ieeecomputersociety.org%2F10.1109%2FiNIS.2015.22 (xsd:string)
dcterms:issued 2015 (xsd:gYear)
rdfs:label Effect of Gate and Channel Engineering on Digital Performance Parameters Using Tied (3T) and Independent (4T) Double Gate MOSFETs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Neha_Jagwani>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Santosh_Kumar_Vishvakarma>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vikas_Vijayvargiya>
swrc:pages 243-247 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ises/2015>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ises/JagwaniVV15/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ises/JagwaniVV15>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ises/inis2015.html#JagwaniVV15>
rdfs:seeAlso <https://doi.ieeecomputersociety.org/10.1109/iNIS.2015.22>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ises>
dc:title Effect of Gate and Channel Engineering on Digital Performance Parameters Using Tied (3T) and Independent (4T) Double Gate MOSFETs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document