A 40nm Low Power High Stable SRAM Cell Using Separate Read Port and Sleep Transistor Methodology.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/ises/MishraSMG18
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A 40nm Low Power High Stable SRAM Cell Using Separate Read Port and Sleep Transistor Methodology.
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A 40nm Low Power High Stable SRAM Cell Using Separate Read Port and Sleep Transistor Methodology.
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