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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ises/RamkumarGRPB20>
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dc:creator <https://dblp.l3s.de/d2r/resource/authors/D._Gracin>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/E._Ramkumar>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/P._Rajkamal>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/V._S._Kanchana_Bhaaskaran>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FiSES50453.2020.00069>
foaf:homepage <https://doi.org/10.1109/iSES50453.2020.00069>
dc:identifier DBLP conf/ises/RamkumarGRPB20 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FiSES50453.2020.00069 (xsd:string)
dcterms:issued 2020 (xsd:gYear)
rdfs:label Design and Analysis of Low Power and High Speed FinFET based Hybrid Full Adder/Subtractor Circuit (FHAS). (xsd:string)
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foaf:maker <https://dblp.l3s.de/d2r/resource/authors/E._Ramkumar>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/P._Rajkamal>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/V._S._Kanchana_Bhaaskaran>
swrc:pages 281-284 (xsd:string)
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rdfs:seeAlso <https://doi.org/10.1109/iSES50453.2020.00069>
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dc:title Design and Analysis of Low Power and High Speed FinFET based Hybrid Full Adder/Subtractor Circuit (FHAS). (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document