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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/isia/ZhouC10>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Haiping_Zhou>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shao-hong_Cai>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-3-642-19853-3%5F36>
foaf:homepage <https://doi.org/10.1007/978-3-642-19853-3_36>
dc:identifier DBLP conf/isia/ZhouC10 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-3-642-19853-3%5F36 (xsd:string)
dcterms:issued 2010 (xsd:gYear)
rdfs:label FPGA Chip Optimization Based on Small-World Network Theory. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Haiping_Zhou>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shao-hong_Cai>
swrc:pages 245-251 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/isia/2010>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/isia/ZhouC10/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/isia/ZhouC10>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/isia/isia2010.html#ZhouC10>
rdfs:seeAlso <https://doi.org/10.1007/978-3-642-19853-3_36>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/isia>
dc:title FPGA Chip Optimization Based on Small-World Network Theory. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document