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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/isia2/LiLLYY23>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jiahuan_Long>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Qingsheng_Li>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shunji_Yang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yujie_Yang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zhen_Li>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F3632314.3632350>
foaf:homepage <https://doi.org/10.1145/3632314.3632350>
dc:identifier DBLP conf/isia2/LiLLYY23 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F3632314.3632350 (xsd:string)
dcterms:issued 2023 (xsd:gYear)
rdfs:label Resource Optimization Method based on CPU-FPGA Mixed-Step Real-Time Simulation. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jiahuan_Long>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Qingsheng_Li>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shunji_Yang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yujie_Yang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zhen_Li>
swrc:pages 31:1-31:5 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/isia2/2023>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/isia2/LiLLYY23/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/isia2/LiLLYY23>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/isia2/isia2023.html#LiLLYY23>
rdfs:seeAlso <https://doi.org/10.1145/3632314.3632350>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/isia2>
dc:title Resource Optimization Method based on CPU-FPGA Mixed-Step Real-Time Simulation. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document