Energy efficient implementation of parallel CMOS multipliers with improved compressors.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/islped/BaranAO10
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2010
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Energy efficient implementation of parallel CMOS multipliers with improved compressors.
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VLSI, arithmetic and logic structures, booth encoding, high- speed arithmetic, low-power design
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Energy efficient implementation of parallel CMOS multipliers with improved compressors.
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