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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/islped/CalhounWVC06>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Alice_Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Anantha_P._Chandrakasan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Benton_H._Calhoun>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Naveen_Verma>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1165573.1165661>
foaf:homepage <https://doi.org/10.1145/1165573.1165661>
dc:identifier DBLP conf/islped/CalhounWVC06 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1165573.1165661 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
rdfs:label Sub-threshold design: the challenges of minimizing circuit energy. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Alice_Wang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Anantha_P._Chandrakasan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Benton_H._Calhoun>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Naveen_Verma>
swrc:pages 366-368 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/islped/2006>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/islped/CalhounWVC06/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/islped/CalhounWVC06>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/islped/islped2006.html#CalhounWVC06>
rdfs:seeAlso <https://doi.org/10.1145/1165573.1165661>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/islped>
dc:subject dynamic voltage scaling, low voltage memory, process variations, sub-threshold digital circuits, sub-threshold logic (xsd:string)
dc:title Sub-threshold design: the challenges of minimizing circuit energy. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document