A power-aware SWDR cell for reducing cache write power.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/islped/ChangYL03
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2003
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A power-aware SWDR cell for reducing cache write power.
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SRAM, cache, circuit-level, low power, write power
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A power-aware SWDR cell for reducing cache write power.
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