Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/islped/ChenRK03
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2003
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Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors.
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inductive noise, power supply noise
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Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors.
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