UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra low-power CMOS VLSI.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/islped/ChoiC03
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/islped/ChoiC03
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Abhijit_Chatterjee
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Kyu-won_Choi
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1145%2F871506.871527
>
foaf:
homepage
<
https://doi.org/10.1145/871506.871527
>
dc:
identifier
DBLP conf/islped/ChoiC03
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1145%2F871506.871527
(xsd:string)
dcterms:
issued
2003
(xsd:gYear)
rdfs:
label
UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra low-power CMOS VLSI.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Abhijit_Chatterjee
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Kyu-won_Choi
>
swrc:
pages
72-77
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/islped/2003
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/islped/ChoiC03/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/islped/ChoiC03
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/islped/islped2003.html#ChoiC03
>
rdfs:
seeAlso
<
https://doi.org/10.1145/871506.871527
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/islped
>
dc:
subject
device and interconnect co-optimization, low-power design, nanometer design, time slack distribution
(xsd:string)
dc:
title
UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra low-power CMOS VLSI.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document