A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/islped/ChunJK09
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A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM.
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3T DRAM, cache, embedded DRAM, gain cell, retention time, static power
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A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM.
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