Improving Performance and Power by Co-Optimizing Middle-of-Line Routing, Pin Pattern Generation, and Contact over Active Gates in Standard Cell Layout Synthesis. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dcterms:bibliographicCitation	<http://dblp.uni-trier.de/rec/bibtex/conf/islped/ChungJK22>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Jooyeon_Jeong>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Sehyeon_Chung>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Taewhan_Kim>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1145%2F3531437.3539712>
foaf:homepage	<https://doi.org/10.1145/3531437.3539712>
dc:identifier	DBLP conf/islped/ChungJK22 (xsd:string)
dc:identifier	DOI doi.org%2F10.1145%2F3531437.3539712 (xsd:string)
dcterms:issued	2022 (xsd:gYear)
rdfs:label	Improving Performance and Power by Co-Optimizing Middle-of-Line Routing, Pin Pattern Generation, and Contact over Active Gates in Standard Cell Layout Synthesis. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Jooyeon_Jeong>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Sehyeon_Chung>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Taewhan_Kim>
swrc:pages	17:1-17:6 (xsd:string)
dcterms:partOf	<https://dblp.l3s.de/d2r/resource/publications/conf/islped/2022>
owl:sameAs	<http://bibsonomy.org/uri/bibtexkey/conf/islped/ChungJK22/dblp>
owl:sameAs	<http://dblp.rkbexplorer.com/id/conf/islped/ChungJK22>
rdfs:seeAlso	<http://dblp.uni-trier.de/db/conf/islped/islped2022.html#ChungJK22>
rdfs:seeAlso	<https://doi.org/10.1145/3531437.3539712>
swrc:series	<https://dblp.l3s.de/d2r/resource/conferences/islped>
dc:title	Improving Performance and Power by Co-Optimizing Middle-of-Line Routing, Pin Pattern Generation, and Contact over Active Gates in Standard Cell Layout Synthesis. (xsd:string)
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rdf:type	swrc:InProceedings
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