The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/islped/EiseleBSM96
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The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits.
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The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits.
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