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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/islped/El-EssawyAS02>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Balaram_Sinharoy>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/David_H._Albonesi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wael_El-Essawy>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F566408.566477>
foaf:homepage <https://doi.org/10.1145/566408.566477>
dc:identifier DBLP conf/islped/El-EssawyAS02 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F566408.566477 (xsd:string)
dcterms:issued 2002 (xsd:gYear)
rdfs:label A microarchitectural-level step-power analysis tool. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Balaram_Sinharoy>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/David_H._Albonesi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wael_El-Essawy>
swrc:pages 263-266 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/islped/2002>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/islped/El-EssawyAS02/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/islped/El-EssawyAS02>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/islped/islped2002.html#El-EssawyAS02>
rdfs:seeAlso <https://doi.org/10.1145/566408.566477>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/islped>
dc:subject Ldi/dt, architectural simulation, clock-gating, inductive noise, microprocessors, step-power (xsd:string)
dc:title A microarchitectural-level step-power analysis tool. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document