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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/islped/FujiwaraNMMMKY06>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hidehiro_Fujiwara>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hiroshi_Kawaguchi_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Junichi_Miyakoshi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Koji_Nii>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Masahiko_Yoshimoto>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yasuhiro_Morita>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yuichiro_Murachi>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1165573.1165589>
foaf:homepage <https://doi.org/10.1145/1165573.1165589>
dc:identifier DBLP conf/islped/FujiwaraNMMMKY06 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1165573.1165589 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
rdfs:label A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hidehiro_Fujiwara>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hiroshi_Kawaguchi_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Junichi_Miyakoshi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Koji_Nii>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Masahiko_Yoshimoto>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yasuhiro_Morita>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yuichiro_Murachi>
swrc:pages 61-66 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/islped/2006>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/islped/FujiwaraNMMMKY06/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/islped/FujiwaraNMMMKY06>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/islped/islped2006.html#FujiwaraNMMMKY06>
rdfs:seeAlso <https://doi.org/10.1145/1165573.1165589>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/islped>
dc:subject data-bit reordering, low power SRAM, majority logic, real-time image processing, two-port SRAM (xsd:string)
dc:title A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document