An empirical comparison of algorithmic, instruction, and architectural power prediction models for high performance embedded DSP processors. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Catherine_H._Gebotys>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Robert_J._Gebotys>
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dc:title	An empirical comparison of algorithmic, instruction, and architectural power prediction models for high performance embedded DSP processors. (xsd:string)
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