Circuit-level techniques to control gate leakage for sub-100nm CMOS.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/islped/HamzaogluS02
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2002
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Circuit-level techniques to control gate leakage for sub-100nm CMOS.
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MTCMOS, domino circuits, gate leakage, low power
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Circuit-level techniques to control gate leakage for sub-100nm CMOS.
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