LAP: a logic activity packing methodology for leakage power-tolerant FPGAs.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/islped/HassanAE05
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2005
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LAP: a logic activity packing methodology for leakage power-tolerant FPGAs.
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FPGA, activity profile, basic logic elements (BLEs), configurable logic blocks (CLBs), packing, sleep transistor (ST), sub-threshold leakage power
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LAP: a logic activity packing methodology for leakage power-tolerant FPGAs.
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