Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dcterms:bibliographicCitation	<http://dblp.uni-trier.de/rec/bibtex/conf/islped/HwangJR07>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Kaushik_Roy_0001>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Myeong-Eun_Hwang>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Seong-Ook_Jung>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1145%2F1283780.1283865>
foaf:homepage	<https://doi.org/10.1145/1283780.1283865>
dc:identifier	DBLP conf/islped/HwangJR07 (xsd:string)
dc:identifier	DOI doi.org%2F10.1145%2F1283780.1283865 (xsd:string)
dcterms:issued	2007 (xsd:gYear)
rdfs:label	Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Kaushik_Roy_0001>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Myeong-Eun_Hwang>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Seong-Ook_Jung>
swrc:pages	387-390 (xsd:string)
dcterms:partOf	<https://dblp.l3s.de/d2r/resource/publications/conf/islped/2007>
owl:sameAs	<http://bibsonomy.org/uri/bibtexkey/conf/islped/HwangJR07/dblp>
owl:sameAs	<http://dblp.rkbexplorer.com/id/conf/islped/HwangJR07>
rdfs:seeAlso	<http://dblp.uni-trier.de/db/conf/islped/islped2007.html#HwangJR07>
rdfs:seeAlso	<https://doi.org/10.1145/1283780.1283865>
swrc:series	<https://dblp.l3s.de/d2r/resource/conferences/islped>
dc:subject	gate delay, interconnect, signal slope, subthreshold operation (xsd:string)
dc:title	Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates. (xsd:string)
dc:type	<http://purl.org/dc/dcmitype/Text>
rdf:type	swrc:InProceedings
rdf:type	foaf:Document