Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Kiyoo_Itoh_0001>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1145%2F1594233.1594298>
foaf:homepage	<https://doi.org/10.1145/1594233.1594298>
dc:identifier	DBLP conf/islped/Itoh09 (xsd:string)
dc:identifier	DOI doi.org%2F10.1145%2F1594233.1594298 (xsd:string)
dcterms:issued	2009 (xsd:gYear)
rdfs:label	Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Kiyoo_Itoh_0001>
swrc:pages	273-274 (xsd:string)
dcterms:partOf	<https://dblp.l3s.de/d2r/resource/publications/conf/islped/2009>
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rdfs:seeAlso	<http://dblp.uni-trier.de/db/conf/islped/islped2009.html#Itoh09>
rdfs:seeAlso	<https://doi.org/10.1145/1594233.1594298>
swrc:series	<https://dblp.l3s.de/d2r/resource/conferences/islped>
dc:subject	0.5-v nanoscale cmos lsis, conventional mosfet, dram, finfet, leakage, minimum vdd, speed variation, sram, vt variation (xsd:string)
dc:title	Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era. (xsd:string)
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